1. Field of the Invention
The present invention relates to an integrated circuit and a standard cell of an integrated circuit.
2. Description of the Background Art
Sequential circuits for performing logic operations with the additional ability to store individual variable states are known from U. Tietze and Ch. Schenk, “Halbleiterschaltungstechnik” (Semiconductor Technology), 12th edition, 2002, pages 675 to 681. For integrated circuits, flip-flops are provided which are subdivided into transparent flip-flops and flip-flops with buffer storage. A master-slave flip-flop with a master flip-flop (master) and a slave flip-flop (slave) can be provided for buffer storage. It can be formed as a two-edge-triggered flip-flop. The flip-flops can be realized, for example, with inverters, NAND gates, or NOR gates as feedback inverting elements.
An edge-triggered D flip-flop as an implementation with transmission gates is known from “CMOS—Circuit Design, Layout, and Simulation,” R. J. Baker et al., IEEE PRESS, 1998, page 270. A D flip-flop can be, for example, a standard cell, as is described on page 291. Standard cells are designed for a manufacturing process and measured and characterized with suitable test structures even before the startup of mass production. Thereby, the complete circuit properties of the cell over the planned operating range (voltage, temperature) are determined and transformed into suitable simulation models. A plurality of cells is combined in this regard into a cell library.